1. Field of the Invention
The present invention relates to a control method and a control system in a three-level inverter which outputs an AC voltage in three levels converted from a DC voltage by carrying out the switching of the DC voltage with the use of semiconductor switching elements, the control method and the control system enabling the inverter to reduce the number of times of the switching and to expand the range of the output voltage.
2. Background Art
FIG. 13 is a circuit diagram showing the circuit configuration of an example of a common three-level inverter with respect to the circuit of one phase. Here, for simplifying the explanation, the circuit configuration with respect to only one phase (U-phase) of the output circuits of three phases is shown.
In FIG. 13, the three-level inverter is provided with DC power supplies 101 and 102 (letting each of the voltage values thereof be Ed), semiconductor switching elements S1 to S4 such as IGBTs and diodes D1 and D2. Signs N and U designate a neutral point and an output terminal, respectively. In the following explanations, in a DC circuit, the positive electrode of the DC power supply 101, the negative electrode of the DC power supply 102 and the neutral point N are to be also referred to as a high voltage point, a low voltage point and a middle voltage point, respectively. Moreover, the voltage Ed, the voltage −Ed and a voltage 0 are to be referred to as a DC high voltage, a DC low voltage and a DC middle voltage, respectively.
In the three-level inverter, by the turning-on and -off operations of the semiconductor switching elements S1 to S4 connected in series and the action of the diodes D1 and D2, it is possible to output the voltages at three levels in the DC circuit, namely the voltages Ed, 0, and −Ed (here, the voltages drop at each element is ignored).
For example, with the semiconductor switching elements S1 and S2 being turned-on and the semiconductor switching elements S3 and S4 being turned-off, an output voltage becomes Ed, with the semiconductor switching elements S2 and S3 being turned-on and the semiconductor switching elements S1 and S4 being turned-off, an output voltage becomes 0, and with the semiconductor switching elements S3 and S4 being turned-on and the semiconductor switching elements S1 and S2 being turned-off, an output voltage becomes −Ed.
FIG. 14 is a circuit diagram showing the circuit configuration of another example of a common three-level inverter with respect to the circuit of one phase.
In FIG. 14, the configuration of the circuit of a three-level inverter is shown with respect to one phase in which inverter the diodes D1 and D2 in the three-level inverter shown in FIG. 13 are omitted and a bidirectional switch S23 formed of the semiconductor switching elements S2 and S3 is used.
The levels of the output voltages of the three-level inverter are the same as the levels of the output voltages of the three-level inverter shown in FIG. 13. For example, with the semiconductor switching element S1 being turned-on and with the semiconductor switching elements S2 to S4 being turned-off, the output voltage becomes Ed, with the semiconductor switching elements S2 and S3 being turned-on and with the semiconductor switching elements S1 and S4 being turned-off, the output voltage becomes 0, and with the semiconductor switching element S4 being turned-on and with the semiconductor switching elements S1 to S3 being turned-off, the output voltage becomes −Ed.
In this way, the three-level inverter, by outputting voltages at three levels, can relax an abrupt change in a voltage applied to a load compared with a two-level inverter. In particular, when a motor is connected as a load, such a three-level inverter is effective in inhibiting a surge voltage to allow the three-level inverter to be widely used.
Here, for a control method of a three-level inverter, there is the method described in each of JP-A-2007-282484 (paragraphs [0008] to [0028] and FIG. 1 to FIG. 3, etc.) and JP-A-2010-206931 (paragraphs [0027] to [0036] and FIG. 1 to FIG. 3, etc.).
In JP-A-2007-282484 (paragraphs [0008] to [0028] and FIG. 1 to FIG. 3, etc.), a method is described in which an output voltage is provided on the basis of the frequency command or the amplitude command of an output voltage command with a dipolar modulation method carried out in a low output voltage region, a unipolar modulation method carried out in a middle output voltage region and an over modulation method carried out in a high output voltage region other than the former two regions, and control is carried out by switching the modulation methods according to the output voltage region.
In JP-A-2010-206931 (paragraphs [0027] to [0036] and FIG. 1 to FIG. 3, etc.), a control method is disclosed in which a plurality of output voltage vectors suited for an output voltage command are selected with the use of instantaneous space vectors and the selected vectors are made to be outputted in the order for preventing common mode voltages, with suggestion of making the voltage vectors cause transition so as not to increase the number of switching operations more than that being necessary.